HSSIO gives a boost to boundary scan
With more and more types of electronic systems incorporating high-speed serial I/O (HSSIO) buses, system designers and test engineers are turning to JTAG because, quite simply, they have no where else to turn. Ironically, validating or testing a design with one of the newer serial buses requires the same sort of capabilities for which the original IEEE 1149.1 Boundary Scan Standard was developed more than 15 years ago. Specifically, physical access to a HSSIO bus is practically prohibited because the contact of a metal probe on a HSSIO bus causes its own signal anomalies, making the readings of test instruments practically useless. That plays right into the strength of JTAG and its access-free test capabilities.
Buses like PCI Express, Serial RapidIO, Serial Advance Technology Attachment (SATA), Mobile Display Digital Interface (MDDI) and others have data throughput speeds that reach upwards to the five to 10 Gbps range. These types of HSSIO buses rely on serializer/deserializer (serdes) technology in their bus interfaces.
Just like all electronic assemblies, PCBs with HSSIO buses require validation and testing beginning with prototype validation and continuing through manufacturing and field service. This testing comes in two forms, structurally validating the physical integrity of an assembly and functionally verifying that the assembly does what it was supposed to do and in the way that it was supposed to do it. Boundary scan has a long and deep history with structural test, but its deployment in functional test has been limited. It remains to be seen, but HSSIO buses could thrust boundary scan into functional test in a bigger way.
To probe or not to probe?
For years, physical probing has been a mainstay of both structural and functional testing. Test systems and instruments such as oscilloscopes, logic analyzers, in-circuit test (ICT), flying probe, manufacturing defect analyzers and others all rely on establishing electrical contact between the unit-under-test and the test system or instrument. The applicability of these types of test systems began changing 15 or so years ago when the density of PCBs increased considerably and physical access to fine-pitch semiconductor device pins became problematic.
Over the intervening years, physical access, or the lack thereof, has been further exacerbated by the shift to several types of device packages such as ball grid arrays (BGA), which totally deny access to pins by placing them underneath the silicon. System-in-packages (SIP) are also impossible to probe since the interconnects between dies are embedded inside the package. In addition, the density of PCBs has only increased over the years, driving designers to multi-layer circuit boards which deny physical access to all but the top-layer device interconnect nets.
Now, high-performance HSSIO buses are adding another set of reasons why physically probing a PCB is becoming impractical in many, if not most, validation and test applications.
PCI Express provides an example. To acquire accurate measurements of signal integrity without being misled by signal attenuation or reflections on a line, measurements on a PCI Express bus must be taken as close as possible to the transmitters or receivers on the line. On prototype circuit boards, this is usually accomplished with small test pads that provide access to physical probes. Unfortunately, these pads create noise on the PCI Express bus and are usually removed on production circuit boards. In general, when oscilloscope and logic analyzer probes are applied to a PCI Express interconnect as well as the other HSSIO buses, they introduce capacitance on a line that probably has a very low tolerance of just a few picofarads (pF) of additional capacitance. If the capacitance on the HSSIO line were to exceed its tolerances, it would cause an impedance discontinuity which would adversely affect signal integrity. When this is the case, the test engineer can not determine whether the UUT has a problem with signal integrity or whether the test probe itself caused the problem.
Structural and functional HSSIO testing
Circuit boards, either prototypes or production boards, with HSSIO buses require both functional and structural at-speed testing to validate designs and locate structural faults. Several relatively new test methodologies are being deployed as alternatives to physically probing a circuit board. Structural testing can be based on the new IEEE 1149.6-2003 Standard on Boundary Scan Testing of Advanced Digital Networks while functional testing is increasingly turning to built-in self test (BIST) engines embedded into semiconductor devices.
Structural and Functional
The 1149.6 standard calls for a modified boundary-scan cell and a special test receiver embedded in semiconductor devices. The cell is upstream of the differential driver on the HSSIO bus and it is capable of placing a single pulse or train of pulses on an individual lane of the differential pair. The special receiver on the lane is capable of determining whether the AC signal is rising or falling. The incoming AC test signal is digitized and the results captured in a standard 1149.1 cell. This process forms the basis for 1149.6 structural testing for opens and shorts, but not functional performance.
ScanWorks' 1149.6 user interface
To perform functional tests on HSSIO buses, several new techniques involving the embedding of BIST engines are being investigated and developed. In one case, that of Intel® Interconnect Built In Self Test (IBIST), the methodology is already being deployed in some of that company’s next-generation processors. IBIST makes use of the 1149.1 boundary-scan infrastructure to provide access to the BIST engines or instruments that Intel has embedded in its chips. In fact, ScanWorks® is the only boundary-scan system that supports IBIST technology.
Besides Intel, several other companies such as Procket Networks (now part of Cisco) and National Semiconductor have announced their intentions for supporting some sort of embedded BIST engines. In addition, an IEEE working group has formed to study the feasibility of developing an open standard for controlling and accessing embedded instruments. This preliminary standard has been designated as the IEEE P1687 Draft Standard for Access and Control of Instrumentation Embedded Within a Semiconductor Device. It is commonly referred to as Internal JTAG or simply IJTAG because it relies upon the JTAG infrastructure in chips and on boards for the physical access layer to embedded instruments.
The P1687 study group is concerning itself with access layer issues and not the features, functionality or operations of the embedded instruments or BIST engines. So far, the IJTAG working group has looked into the hardware interface to internal instrumentation. The group is now turning its attention to a language that would characterize embedded instruments. This language would also help finalize the interface or interfaces to embedded instruments.
Based on boundary-scan
Even though the various test methods for HSSIO buses will continue to evolve over the near term, one aspect of these methodologies appears certain. That is, boundary-scan technology and its embedded infrastructure will play pivotal roles in the structural and functional testing of next-generation high-speed buses.